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IR3529
DATA SHEET XPHASE3TM PHASE IC
DESCRIPTION
The IR3529 Phase IC combined with an IR XPhase3 Control IC provides a full featured and flexible way to implement power solutions for the latest high performance CPUs and ASICs. The "Control" IC provides overall system control and interfaces with any number of "Phase" ICs which each drive and monitor a single phase of a TM multiphase converter. The XPhase3 architecture results in a power supply that is smaller, less expensive, and easier to design while providing higher efficiency than conventional approaches. The IR3529 provides two types of current sense outputs; ILL which contains average power supply current, information which can be used for voltage positioning and ISHARE which contains average active phase current information since current sense amplifiers of respective phases are disabled when in power savings mode. Higher efficiency can be expected due to increased driver capability along with reduced non-overlap durations. Turbo is included to improve load turn-on response. A SHIFT pin now communicates to the control IC a change in phase IC on-line status resulting in controlled phase timing during PSI and Phase Shedding. The IR3529 also implements cycle-by-cycle over current protection to resolve high repetition rate load transients.
TM
FEATURES
* * * * * * * * * * * * * * * * * * * * * Reduced dead time 7V gate drivers (6A GATEL sink current, 4A GATEH sink current) Turbo Mode load turn-on response enhancement Programmable cycle-by-cycle over current limit protection Phase status communicated to control IC for controlled phase timing during PSI and Phase Shedding Power State Indicator (PSI) interface provides the capability to maximize the efficiency at light loads. Anti-bias circuitry Support converter output voltage up to 5.1 V (Limited to VCCL-1.8V) Loss-less inductor current sensing Phase delay DFF bypassed during PSI assertion mode to improve output ripple performance Over-current protection during PSI assertion mode operation Feed-forward voltage mode control Integrated boot-strap synchronous PFET Only four external components per phase 3 wire analog bus connects Control and Phase ICs (VID, Error Amp, Average Power Supply Current) 3 wire digital bus for accurate daisy-chain phase timing control without external components Debugging function isolates phase IC from the converter Self-calibration of PWM ramp, current sense amplifier, and current share amplifier Single-wire bidirectional average current sharing Small thermally enhanced 20L 4 X 4mm MLPQ package RoHS compliant
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IR3529
APPLICATION CIRCUIT
12V VCCL EAIN 18 19 20 17 16 ISHARE ROCSET COCSET RCS SW GATEH 15 14 13 12 11 CVCCL1 VOUTCBST COUT L VOUT+ CCS
ISHARE
CSIN+
CSIN-
ILL PSI# DACIN
1 2 3 4 5
ILL PSI# DACIN LGND
EAIN
IR3529
PHSOUT
VCC BOOST VCCL GATEL 10 OCSET
PHSIN SHIFT
CLKIN 8
PHSIN 6 7 SHIFT PHSOUT CLKIN 9
Figure 1 Single Phase Application Circuit
ORDERING INFORMATION
Part Number IR3529MTRPBF * IR3529MPBF * Samples only Package 20 Lead MLPQ (4 x 4 mm body) 20 Lead MLPQ (4 x 4 mm body) Order Quantity 3000 per reel 100 piece strips
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PGND
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IR3529
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. Operating Junction Temperature................. 0 to 150 C o o Storage Temperature Range......................-65 C to 150 C MSL Rating.............................................2 o Reflow Temperature..................................260 C PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Note: 1. 2. 3. 4. PIN NAME ILL PSI# DACIN LGND PHSIN SHIFT PHSOUT CLKIN PGND GATEL OCSET VCCL BOOST GATEH SW VCC CSIN+ CSINEAIN ISHARE Maximum Maximum Maximum Maximum VMAX 7.5V 7.5V 3.3V n/a 7.5V 7.5V 7.5V 7.5V 0.3V 7.5V 25V 7.5V 40V 40V 34V 25V 7.5V 7.5V 7.5V 7.5V VMIN -0.3V -0.3V -0.3V n/a -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V DC, -5V for 100ns -0.3V -0.3V -0.3V -0.3V DC, -5V for 100ns -0.3V DC, -5V for 100ns -0.3V -0.3V -0.3V -0.3V -0.3V ISOURCE 1mA 1mA 1mA n/a 1mA 2mA 2mA 1mA 5A for 100ns, 200mA DC 5A for 100ns, 200mA DC 1mA n/a 1A for 100ns, 100mA DC 3A for 100ns, 100mA DC 3A for 100ns, 100mA DC n/a 1mA 1mA 1mA 1mA ISINK 1mA 1mA 1mA n/a 1mA 2mA 2mA 1mA n/a 5A for 100ns, 200mA DC 1mA 5A for 100ns, 200mA DC 3A for 100ns, 100mA DC 3A for 100ns, 100mA DC n/a 10mA 1mA 1mA 1mA 1mA
o
GATEH - SW = 8V BOOST - GATEH = 8V OCSET = VCC SW - VCC = 9V
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IR3529
RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN
8.0V VCC 16V, 4.75V VCCL 7.5V, 0 C TJ 125 C. 0.5V V(DACIN) 1.6V, 500kHz CLKIN 9MHz, 250kHz PHSIN 1.5MHz.
o o
ELECTRICAL CHARACTERISTICS
The electrical characteristics involve the spread of values guaranteed within the recommended operating conditions. Typical values represent the median values, which are related to 25C. CGATEH = 3.3nF, CGATEL = 6.8nF (unless otherwise specified) PARAMETER Gate Drivers GATEH Source Resistance GATEH Sink Resistance GATEL Source Resistance GATEL Sink Resistance GATEH Source Current GATEH Sink Current GATEL Source Current GATEL Sink Current GATEL low to GATEH high delay GATEH low to GATEL high delay PWM Comparator PWM Ramp Slope EAIN Bias Current Minimum Pulse Width Minimum GATEH Turn-off Time Daisy Chain Timing CLKIN Bias Current CLKIN Phase Delay PHSIN Pull-Down Resistance PHSOUT High Voltage PHSOUT Low Voltage Down SHIFT Pulse width Up SHIFT Pulse width SHIFT Resistance to Rails Current Sense Amplifier CSIN+/- Bias Current TEST CONDITION BOOST - SW = 7V. BOOST - SW = 7V. VCCL - PGND = 7V. VCCL - PGND = 7V. BOOST=7V, GATEH=2.5V, SW=0V. BOOST=7V, GATEH=2.5V, SW=0V. VCCL=7V, GATEL=2.5V, PGND=0V. VCCL=7V, GATEL=2.5V, PGND=0V. BOOST = VCCL = 7V, SW = PGND = 0V, measure time from GATEL falling to 1V to GATEH rising to 1V BOOST = VCCL = 7V, SW = PGND = 0V, measure time from GATEH falling to 1V to GATEL rising to 1V Vin=12V 0 EAIN 3V Note 1 MIN TYP 670 670 670 300 3 4 4 6 5 15 25 MAX UNIT m m m m A A A A ns
5
15
25
ns
42 -25 20
52.5 -15 55 80 0.0 75 100 0.6 0.4 50 50 50
57 -5 70 160 0.5 125 170
mV/ %DC A ns ns
CLKIN = V(VCCL) Measure time from CLKIN<1V to GATEH>1V
-0.5 40 30
A ns k V
I(PHSOUT)=-10mA, measure VCCL- PHSOUT I(PHSOUT) = 10mA 47pF load, 27% VCCL 47pF load, 77% VCCL
1 25 25 20
1 75 75 80
V ns ns k
I(CSINM) measured with I(CSINM) sink turned off (i.e. within 8us of CLKIN fall and EAIN above Body Brake Threshold and CSINM above 75% DACIN)
-200
0
200
nA
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PARAMETER SW Floating Voltage TEST CONDITION Measured in the application with the converter not switching. Measure after 50us of CLKIN=0 with CSINM shorted to SW CSIN+ = CSIN- = DACIN. Measure input referred offset from DACIN. Note1 0.5V V(DACIN) < 1.6V 0.8V V(DACIN) 1.6V, Note 1 0.5V V(DACIN) < 0.8V, Note 1 Note 1 MIN 10 -450 31.0 -10 -5 0 3.6 3.6 I(CSINM) measured with I(CSINM) sink turned off (i.e. within 8us of CLKIN fall and EAIN above Body Brake Threshold and CSINM above 75% DACIN) Measured in the application with the converter not switching. Measure after 50us of CLKIN=0 with CSINM shorted to SW CSIN+ = CSIN- = DACIN. Measure input referred offset from DACIN. Note1 0.5V V(DACIN) < 1.6V 0.8V V(DACIN) 1.6V, Note 1 0.5V V(DACIN) < 0.8V, Note 1 Note 1 4.7 4.7 32.5 TYP 100 MAX 250 +450 34.5 50 50 VCCL - 2.5V 5.4 5.4 UNIT mV
Calibrated Input Offset Voltage GAIN Differential Input Range Differential Input Range Common Mode Input Range ILL Rout at TJ = 125 C ISHARE Rout at TJ =125 C Current Sense Amplifier CSIN+/- Bias Current
V
V/V mV mV V k k
-200
0
200
nA
SW Floating Voltage
10 -450 31.0 -10 -5 0 3.6
100
250 +450
mV
Calibrated Input Offset Voltage Gain Differential Input Range Differential Input Range Common Mode Input Range o ILL Rout at TJ = 125 C ISHARE Rout at TJ =125 C Share Adjust Amplifier Maximum PWM Ramp Floor Voltage Minimum PWM Ramp Floor Voltage Body Brake Comparator Threshold Voltage with EAIN decreasing Threshold Voltage with EAIN increasing Hysteresis Body Brake Comparator Threshold Voltage with EAIN decreasing Threshold Voltage with EAIN increasing Hysteresis Page 5 of 22
o
V
V/V mV mV V k k
32.5
34.5 50 50 VCCL - 2.5V 5.4 5.4
4.7 4.7
3.6 ISHARE = DACIN - 200mV. Measure relative to floor voltage. ISHARE = DACIN + 200mV. Measure relative to floor voltage. Measure relative to Floor Voltage Measure relative to Floor Voltage
120 -220
180 -160
240 -100
mV mV
-300 -200 70
-200 -100 105
-110 -10 130
mV mV mV
Measure relative to Floor Voltage Measure relative to Floor Voltage
-300 -200 70
-200 -100 105
-110 -10 130
mV mV mV
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IR3529
PARAMETER OVP Comparator OVP Threshold Propagation Delay TEST CONDITION Step V(ILL) up until GATEL drives high. Compare to V(VCCL) V(VCCL)=5V, Step V(ILL) up from V(DACIN) to V(VCCL). Measure time to V(GATEL)>4V. MIN -1.0 15 TYP -0.8 40 MAX -0.4 70 UNIT V ns
Synchronous Rectification Disable Comparator Threshold Voltage Over Current Comparator IOCSET Sink Current
The ratio of V(CSIN-) / V(DACIN), below which V(GATEL) is always low. 0C, 100mV66 145 165 242
75 180 231 279 50 260
86 220 240 321 75
% A A A ns mV
Propagation Delay Time Turbo Comparator Activation Threshold Voltage Turbo Pulse Width Turbo Enable Threshold Debug Comparator Threshold Voltage General VCC Supply Current VCCL Supply Current BOOST Supply Current PSI# Comparator Rising Threshold Voltage Falling Threshold Voltage Hysteresis Resistance Floating Voltage
200 66 -250 1.1 3.1 0.5 420 400 50 40 800
400 75 -150 2.0 8.0 1.5 600 530 92.5 100 975
600 86 -50 4 12.5 3 700 650 135 170 1150
ns % mV mA mA mA mV mV mV k mV
Note 1
Note 1: Guaranteed by design, but not tested in production
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IR3529
PIN DESCRIPTION
PIN# 1 PIN SYMBOL ILL PIN DESCRIPTION Output of the Current Sense Amplifier is connected to this pin through a 3k resistor. Voltage on this pin is equal to V(DACIN) + 33 [V(CSIN+) - V(CSIN-)]. Connecting all ILL pins together creates a bus which provides an indication of the average current being supplied by the power supply. The signal is used by the Control IC for voltage positioning and over-current protection. OVP mode is initiated if the voltage on this pin rises above V(VCCL)- 0.8V. Digital Power State Indicator input, active low. Reference voltage input from the Control IC. The Current Sense signal and PWM ramp is referenced to the voltage on this pin. Ground for internal IC circuits. IC substrate is connected to this pin. Phase clock input at switching frequency. Communication input from phase IC(s) statically floats at VCCL/2. Momentarily pulling pin up to VCCL indicates a phase has entered the daisy chain loop resulting in an up-shift in the CLKOUT frequency. Momentarily pulling down to ground indicates a loss of a phase and down-shifts the CLKOUT frequency. Phase clock output at switching frequency. Clock input. Return for low side driver and reference for GATEH non-overlap comparator. Low-side driver output and input to GATEH non-overlap comparator. Programs cycle by cycle Over Current threshold voltage. V(OCSET) gets compared against the V(SW) node when the high side MOSFET is on. If V(SW) gets below V(OCSET), the next switch pulse gets skipped to allow inductor relaxation. The V(OCSET) threshold is programmed by forcing a 200uA current sink through an external resistor kelvined to the drain of the high side FET. Supply for low-side driver. Internal bootstrap synchronous PFET is connected from this pin to the BOOST pin. Supply for high-side driver. Internal bootstrap synchronous PFET is connected between this pin and the VCCL pin. High-side driver output and input to GATEL non-overlap comparator. Return for high-side driver and reference for GATEL non-overlap comparator. Supply for internal IC circuits. Non-Inverting input to the current sense amplifier, and input to debug comparator. Inverting input to the current sense amplifier, and input to synchronous rectification disable comparator. PWM comparator input from the error amplifier output of Control IC. Body Braking mode is initiated if the voltage on this pin is less than V(DACIN). Output of the Current Sense Amplifier is connected to this pin through a 3k resistor. Voltage on this pin is equal to V(DACIN) + 33 [V(CSIN+) - V(CSIN-)]. Connecting all ISHARE pins together creates a share bus which provides an indication of the average current being supplied by active phases only. The pin becomes high impedance during PSI# activation.
2 3 4 5 6
PSI# DACIN LGND PHSIN SHIFT
7 8 9 10 11
PHSOUT CLKIN PGND GATEL OCSET
12 13 14 15 16 17 18 19 20
VCCL BOOST GATEH SW VCC CSIN+ CSINEAIN ISHARE
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IR3529
SYSTEM THEORY OF OPERATION
System Description The system consists of one control IC and a scalable array of phase converters, each requiring one phase IC. The control IC communicates with the phase ICs using three digital buses, i.e., CLOCK, PHSIN, PHSOUT and three analog buses, i.e., DAC, EA, and IOUT. The digital buses are responsible for switching frequency determination and accurate phase timing control without any external components. The analog buses are used for PWM control and current sharing between interleaved phases. The control IC incorporates all the system functions, i.e., VID, CLOCK signals, error amplifier, fault protections, current monitor, etc. The Phase IC implements the functions required by the converter of each phase, i.e., the gate drivers, PWM comparator and latch, over-voltage protection, phase disable circuit, current sensing and sharing, etc. PWM Control Method The PWM block diagram of the XPhase3 architecture is shown in Figure 1. Feed-forward voltage mode control with trailing edge modulation is used. A high-gain and wide-bandwidth voltage type error amplifier is implemented in the controller's design to achieve a fast voltage control loop. Input voltage is sensed by the phase ICs to provide feedforward control. The feed-forward control compensates the ramp slope based on the change in input voltage. The input voltage can change due to variations in the silver box output voltage or due to the wire and PCB-trace voltage drop related to changes in load current.
GATE DRIVE VOLTAGE
TM
VIN
CONTROL IC
CLOCK GENERATOR CLKOUT PHSOUT
PHSOUT
PHASE IC
CLKIN
CLK Q
VCC VCCH GATEH VOSNS+
PHSIN
D 1 2 PWM COMPARATOR VID6 VID6 & VID6LATCH
CBST
PHSIN SHIFT NO. OF ACTIVE PHASES MONITOR PSI EAIN
VID6 VID6
VID6 OFF
SW VOUT VCCL
COUT
VID6
VID6
GATEL
+
GND VOSNS-
REMOTE SENSE AMPLIFIER
VID6 OFF VO VDAC LGND ILL VID6 SHARE ADJUST VID6 AMPLIFIER VID6
SHIFT PULSE VID6 GENERATION
PGND
+
-
VDAC
+ -
ERROR AMPLIFIER FB
RVSETPT
IROSC IVSETPT
VDAC
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+
VDRP AMP
Thermal Compensation
-
-
BODY BRAKING VID6 VID6
VID6
PSI# COMPARATOR & VID6 8 COUNT DELAY
PSI
EAOUT
RCOMP RFB1 RFB CCOMP CFB1
ISHARE
VID6 CURRENT VID6 SENSE AMPLIFIER VID6
SHIFT CSIN+
CCS RCS
VID6 VID6 +
+
CSIN-
DACIN
RDRP1 RDRP CDRP
VSETPT IMON
PHSOUT
PHASE IC
CLKIN
CLK Q D
VCC VCCH GATEH
CBST
PHSIN VDRP VN
RTHRM 1 2 PWM COMPARATOR VID6 VID6 &
VID6 VID6
VID6 OFF
SW
VID6LATCH VID6 VID6 EAIN
VCCL GATEL VID6 VID6
BODY BRAKING VID6 VID6
IIN
OFF
PGND
VID6 ILL VID6 SHARE ADJUST VID6 AMPLIFIER VID6
PSI# COMPARATOR & VID6 8 COUNT DELAY
PSI
PSI#
SHIFT PULSE VID6 GENERATION
ISHARE
VID6 CURRENT VID6 SENSE VID6 AMPLIFIER
SHIFT CSIN+
CCS RCS
SHIFT
VID6 VID6 +
+
CSIN-
DACIN
Figure 1: PWM Block Diagram
February 12, 2010
IR3529
Frequency and Phase Timing Control The oscillator is located in the Control IC and the system clock frequency is programmable from 250 kHz to 9 MHz by an external resistor. The control IC system clock signal (CLKOUT) is connected to CLKIN of all the phase ICs. The phase timing of the phase ICs is controlled by the daisy chain loop, where the control IC phase clock output (PHSOUT) is connected to the phase clock input (PHSIN) of the first phase IC, and PHSOUT of the first phase IC is connected to PHSIN of the second phase IC, etc. The last phase IC is connected back to PHSIN of the control IC to complete the daisy chain loop. During power up, the control IC sends out clock signals from both CLKOUT and PHSOUT pins and detects the feedback at PHSIN pin to determine the phase number and monitor any fault in the daisy chain loop. When the PSI is asserted (active low), the phases are effectively removed from the daisy chain loop. Figure 2 shows the phase timing for a four phase converter. The switching frequency is set by the resistor ROSC. The clock frequency equals the number of phase times the switching frequency.
Control IC CLKOUT (Phase IC CLKIN) Control IC PHSOUT (Phase IC1 PHSIN) Phase IC1 PWM Latch SET Phase IC 1 PHSOUT (Phase IC2 PHSIN) Phase IC 2 PHSOUT (Phase IC3 PHSIN) Phase IC 3 PHSOUT (Phase IC4 PHSIN) Phase IC4 PHSOUT (Control IC PHSIN)
Figure 2: Four Phase Oscillator Waveforms
PWM Operation The PWM comparator is located in the phase IC. Upon receiving the falling edge of a clock pulse, the PWM latch is set and the PWM ramp voltage begins to increase. In addition, the low side driver is turned off and the high side driver is turned on after the non-overlap time expires (GATEL < 1V). When the PWM ramp voltage exceeds the error amplifier's output voltage, the PWM latch is reset and the internal ramp capacitor is quickly discharged to the output of the share adjust amplifier and remains discharged until the next clock pulse. This reset latch additionally turns off the high side driver and enables the low side driver after the non-overlap time concludes (Switch Node < 1V). The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in response to a load step decrease. Phases can overlap and go up to 100% duty cycle in response to a load step increase with turn-on gated by the clock pulses. An error amplifier output voltage greater than the common mode input range of the PWM comparator, results in 100% duty cycle regardless of the voltage of the PWM ramp. This arrangement guarantees that the error amplifier is always in control and can demand 0 to 100% duty cycle as required. It also favors response to a load step decrease, which is appropriate, given that the low output to input voltage ratio of most systems. The inductor current will increase much more rapidly than decrease in response to load transients. This control method is designed to provide "single cycle transient response." The inductor current will change in response to load transients within a single switching cycle maximizing the effectiveness of the power train and minimizing the output capacitor requirements. An additional advantage of the architecture is that differences in ground or input voltage, at the phases, have no effect on operation since the PWM ramps are referenced to VDAC. Figure 3 depicts PWM operating waveforms under various conditions. Page 9 of 22 February 12, 2010
IR3529
PHASE IC CLOCK PULSE
EAIN PWMRMP VDAC
GATEH
GATEL
STEADY-STATE OPERATION
DUTY CYCLE INCREASE DUE TO LOAD INCREASE
DUTY CYCLE DECREASE DUE TO VIN INCREASE (FEED-FORWARD)
DUTY CYCLE DECREASE DUE TO LOAD DECREASE (BODY BRAKING) OR FAULT (VCCLUV, OCP, VID=11111X)
STEADY-STATE OPERATION
Figure 3: PWM Operating Waveforms Body Braking
TM
In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in response to a load step decrease is;
TSLEW =
L * ( I MAX - I MIN ) VO
The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in response to a load step decrease. The switch node voltage is then forced to decrease until conduction of the synchronous rectifier's body diode occurs. This increases the voltage across the inductor from Vout to Vout + VBODYDIODE. The minimum time required to reduce the current in the inductor in response to a load transient decrease is now;
TSLEW =
L * ( I MAX - I MIN ) VO + VBODYDIODE
Since the voltage drop in the body diode is often comparable to the output voltage, the inductor current slew rate can be increased significantly. This patented technique is referred to as "body braking" and is accomplished through the "body braking comparator" located in the phase IC. If the error amplifier's output voltage drops below the output voltage of the share adjust amplifier in the phase IC, this comparator turns off the low side gate driver. Lossless Average Inductor Current Sensing Inductor current can be sensed by connecting a series resistor and a capacitor network in parallel with the inductor and measuring the voltage across the capacitor, as shown in Figure 4. The equation of the sensing network is,
vC ( s ) = vL ( s)
1 RL + sL = iL ( s ) 1 + sRCS CCS 1 + sRCS CCS
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IR3529
Usually the resistor Rcs and capacitor Ccs are chosen so that the time constant of Rcs and Ccs equals the time constant of the inductor which is the inductance L over the inductor DCR (RL). If the two time constants match, the voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of inductor DC current, but affects the AC component of the inductor current. vL iL L RCS
Current Sense Amp
RL CCS
c vCS
VO CO
CSOUT Figure 4: Inductor Current Sensing and Current Sense Amplifier The advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled information about the switch currents. The output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in series with the inductor, this is the only sense method that can support a single cycle transient response. Other methods provide no information during either load increase (low side sensing) or load decrease (high side sensing). An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer from peak-to-average errors. These errors will show in many ways but one example is the effect of frequency variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and the output impedance of the converter will drop by about 10%. Variations in inductance, current sense amplifier bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all additional sources of peak-toaverage errors. Current Sense Amplifier A high speed differential current sense amplifier is located in the phase IC, as shown in Figure 4. Its gain is nominally 32.5, and the 3850 ppm/C increase in inductor DCR should be compensated in the voltage loop feedback path. The current sense amplifier can accept positive differential input up to 50mV and negative up to -10mV before clipping. The output of the current sense amplifier is summed with the DAC voltage and sent to the control IC and other phases through an on-chip 3K resistor connected to the ILL pin. The output of the current sense amplifier is summed with the DAC voltage and sent to the phases through an on-chip 3K resistor connected to the ISHARE pin. The ILL pins of all the phases are tied together and the voltage on the share bus represents the average current through all the inductors and is used by the control IC for voltage positioning. The ISHARE pins of all the phases are tied together and are not connected to the control IC. The input offset of this amplifier is calibrated to +/- 1mV in order to reduce the current sense error. The input offset voltage is the primary source of error for the current share loop. In order to achieve very small input offset error and superior current sharing performance, the current sense amplifier continuously calibrates itself. This calibration algorithm creates ripple on IOUT bus with a frequency of fsw/896 in a multiphase architecture. Average Current Share Loop Current sharing between phases of the converter is achieved by the average current share loop in each phase IC. The output of the current sense amplifier is compared with the average current at the share bus. If current in a phase is smaller than the average current, the share adjust amplifier of the phase will pull down the starting point of the PWM ramp thereby increasing its duty cycle and output current; if current in a phase is larger than the average current, the Page 11 of 22 February 12, 2010
IR3529
share adjust amplifier of the phase will pull up the starting point of the PWM ramp thereby decreasing its duty cycle and output current. The current share amplifier is internally compensated so that the crossover frequency of the current share loop is much slower than that of the voltage loop and the two loops do not interact. For proper current sharing the output of current sense amplifier should not exceed (VCCL-1.4V) under all operating condition.
IR3529 THEORY OF OPERATION
Block Diagram The Block diagram of the IR3529 is shown in Figure 5, and specific features are discussed in the following sections.
PHSIN
D Q PSI_SY NC PSI_SY NC#
PHSOUT
. . . CLK D Q
CLKIN
.
PSI_SY NC
CLK QB
.
OC
. .
BOOST
Turbo
.
PGND
.
GATEL
EAIN
.
SW
VCC
VCC
.
PWM Comparator. & Latch.
.OC
PWM_RESET
Non-Overlap . Time Generator .
.
.
. . . . . .
VCCL
GATEH Enable
. GATE H Driver
GATEH
GATEH
.
OC
.
. Cycle-byCycle OCP.
OCSET
200uA
100mV 200mV
+ -
BODY BRAKING COMPARATOR
VCCL
SW
LGND
PSI_SY NC# PSI_SY NC
. . . . . . .
GATEL Enable
. GATE L Driver
GATEL PGND
0.8V VCCL
OVP COMPARATOR
+ OVP
SHIFT Pulse Generation
.
SHIFT
SHIFT
SHIFT
DEBUG COMPARATOR 0.15V VCCL
-
ILL
.
.
.
ISHARE
. . . .
.
Share Adjust . Amplifier.
CALIBRATION PHSIN PSI_SY NC CSREF
Negative Current Comparator & Latch .
CURRENT SENSE AMPLIFIER
. . DACIN
.+
CSAOUT CALIBRATION
X33
+ PHSIN
-
+
Figure 5: Block diagram
Tri-State Gate Drivers The gate drivers are design to provide a 2A source and sink peak current (Bottom gate driver can sink 4A). An adaptive non-overlap circuit monitors the voltage on the GATEH and GATEL pins to prevent MOSFET shootthrough current and minimizing body diode conduction. The non-overlap latch is added to eliminate erroneous triggering caused by the switching noise. A fault condition is communicated to the phase IC via the control IC's error amplifier without an additional dedicated signal line. The error amplifier's output is driven low in response to any fault condition detected by the controller, such as VCCL under voltage or output overload, disabling the phase TM TM IC and activating Body Braking . The IR3529 Body Braking comparator detects the low signal at the EAIN and drives the bottom gate output low. This tri-state operation prevents negative inductor current and negative output voltage during power-down.
Page 12 of 22
+
Synchronous Rectification Disable
.
0.75 DACIN
.
CSINCSIN+
.
PSI# Comparator & . 8 Count Delay
PSI#
February 12, 2010
IR3529
A synchronous rectification disable comparator is used to detect the converter's CSIN- pin voltage, which represents local converter output voltage. If the voltage is below 75% of VDAC and negative current is detected, GATEL is driven low, which disables synchronous rectification and eliminates negative current during power-up. The gate drivers are pulled low if the supply voltage falls below the normal operating range. An 80k resistor is connected across the GATEH/GATEL and PGND pins to prevent the GATEH/GATEL voltage from rising due to leakage or other causes under these conditions. PWM Ramp Every time the phase IC is powered up, the PWM ramp magnitude is calibrated to generate a 52.5 mV/% ramp (VCC=12V). For example, a 15 % duty ratio will generate a ramp amplitude of 787.5 mV (15 x 52.5 mV) with 12V supply applied to VCC. Feed-forward control is achieved by varying the PWM ramp proportionally with VCC voltage after calibration. In response to a load step-up, the error amplifier can demand 100 % duty cycle. As shown in Figure 6, 100 % duty is detected by comparing the PWM latch output (PWMQ) and its input clock (PWM_CLK). If the PWMQ is high when the PWM_CLK is asserted, the top FET turnoff is initiated. The top FET is again turned on once the RMPOUT drops within 200 mV of the VDAC.
NORMAL OPERATION 100 % DUTY OPERATION
CLKIN
PHIN (2 Phase Design)
EAIN RMPOUT
PWMQ
Figure 6: PWM Operation during normal and 100 % duty mode. Power State Indicator (PSI) function From a system perspective, the PSI input is controlled by the system and is forced low when the load current is lower than a preset limit and forced high when load current is higher than the preset limit. IR3529 can accept an active low signal on its PSI input and force the drivers into tri-state, effectively, forcing the phase IC into an off state. Once the PSI# signal is asserted, the IC waits for 8 PHSIN cycles before forcing the drivers into tri-state. This delay is required to ensure that the IC does not respond to any high frequency PSI# signal because entering into PSI mode for a very short duration does not benefit the system efficiency. Irrespective of the PSI# input, the disabled phase remains connected to the ILL bus which ensures accurate voltage positioning. However, on assertion of PSI# signal, the disabled phase is disconnected from the ISHARE bus and therefore ISHARE will represent the actual per phase current information.
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February 12, 2010
IR3529
PSI
8 PHSIN Delay
CLK
PSI_SYNC D_PWM LATCH
Figure 7: PSI assertion. Turbo Modulator The turbo functionality is included in IR3529 to improve the transient performance of the system with reduced output capacitance. The turbo modulator consists of a comparator that monitors the EAIN signal and its filtered version. The modulator turns on the phase when EAIN reaches 260 mV above its filtered version and turns off when EAIN reaches its peak value. This action helps to achieve an improved transient response with lesser output capacitors thereby reducing the overall system cost. Cycle-by-cycle over current protection IR3529 incorporates the OCSET function to improve the transient response when the load repetition rate is close to the switching frequency. When a significantly high load current is cycled at the switching frequency of the multiphase VR, the phases that are synchronized with the load current will experience an incremental change in the duty ratio while the other phases will experience a decrease in the duty ratio from the nominal value. This in turn will lead to huge inductor currents in the phases that are synchronized with the load and thereby saturating the inductor core. Eventually, this will lead to an OVP condition or failure of the high-side MOSFET. In IR3529, the problem due to high repetition rate of the load is addressed by high side current sensing and thereby providing cycle-by-cycle over current protection. The over current threshold is programmed with an external resistor (ROCSET) connected to the OCSET pin with a sink current of 200 A. The OCSET comparator monitors the voltage across the on-resistance (RDS, ON) of the high-side MOSFET and terminates the high side pulse if the sensed voltage reaches the over current threshold. This helps to reduce the deviation at the error amplifier output thereby improving the transient response. Debugging Mode If the CSIN+ pin is pulled up to VCCL voltage, IR3529 enters into debugging mode. Both drivers are pulled low and IOUT output is disconnected from the current share bus, which isolates this phase IC from other phases. However, the phase timing from PHSIN to PHSOUT does not change. Emulated Bootstrap Diode IR3529 integrates a PFET to emulate the bootstrap diode. If two or more top MOSFETs are to be driven at higher switching frequency, an external bootstrap diode connected from VCCL pin to BOOST pin may be needed. Page 14 of 22 February 12, 2010
IR3529
OUTPUT VOLTAGE (VO)
OVP THRESHOLD 130mV
VCCL-800 mV
IOUT(ISHARE)
GATEH (PHASE IC)
GATEL (PHASE IC)
FAULT LATCH ERROR AMPLIFIER OUTPUT (EAOUT)
VDAC
NORMAL OPERATION
OVP CONDITION
AFTER OVP
Figure 8: Over-voltage protection waveforms Over Voltage Protection (OVP) The IR3529 includes over-voltage protection that turns on the low side MOSFET to protect the load in the event of a shorted high-side MOSFET, converter out of regulation, or connection of the converter output to an excessive output voltage. As shown in Figure 8, if IOUT pin voltage is above V(VCCL) - 0.8V, which represents over-voltage condition detected by control IC, the over-voltage latch is set. GATEL drives high and GATEH drives low. The OVP circuit overrides the normal PWM operation and within approximately 150ns will fully turn-on the low side MOSFET, which remains in conduction until IOUT drops below V(VCCL) - 0.8V when over voltage ends. The over voltage fault is latched in control IC and can only be reset by cycling the power to control IC. The error amplifier output (EAIN) is pulled down by control IC and will remain low. The lower MOSFETs alone can not clamp the output voltage however a SCR or N-MOSFET could be triggered with the OVP output to prevent processor damage. Operation at Higher Output Voltage The proper operation of the phase IC is ensured for output voltage up to 5.1V. Similarly, the minimum VCC for proper operation of the phase IC is 8 V. Operating below this minimum voltage, the current sharing performance of the phase IC is affected.
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February 12, 2010
IR3529
APPLICATIONS SCHEMATIC
+12V 4.75V to 7.5V VCCL
19
20
18
PSI# VRRDY 1 RMON IOUT CMON RMON1 32 31 29 28 30 27 26 25 CVCCL VOSEN33 1 2 3 4 5 6 7 8 4 5 PHSIN PHSOUT CLKOUT 2 3
17
16
ROCP1 COCP1 RCS1 SW GATEH 15 14 13 12 11 CVCCL2 VOUTCBST1 COUT1 VOSENVOSEN+ L1 VOUT+ CCS1
ISHARE
CSIN+
CSIN-
ILL PSI# DACIN LGND
EAIN
IR3529
PHSOUT
VCC BOOST VCCL GATEL 10 OCSET
VRRDY
CLKIN 8
SHIFT
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
VID7 VID6 VID5 VID4 VID3 VID2 VID1
PSI# ROSC
24 23 22 21 20 19 18 17 RTCMP1 RTHERM 1 2 ILL PSI# DACIN LGND RVDAC RSETPT RTCMP2 ROSC CSS/DEL CVDAC
6
7
SS/DEL
IR3503
VDAC VSETPT VDAC_BUFF VN
9
PGND
EXPAD
SHIFT
VCCL
IMON
IIN
PHSIN
20
19
18
17
16
ROCP2 COCP2 RCS2 SW GATEH 15 14 13 12 11 CVCCL3 CBST2 L2 CCS2
CSIN-
ISHARE
CSIN+
VOSEN+
ENABLE
VOSEN-
VRHOT
EAOUT
VID0
HOTSET
VDRP
VO
FB
10
11
12
13
14
15
16
RTCMP3 RDRP 3 4
ENABLE VRHOT RHOTSET2
9
EAIN
IR3529
PHSOUT
VCC BOOST VCCL GATEL 10 OCSET
5
PHSIN SHIFT
CLKIN 8
6
7
RHOTSET1
RFB RFB1
CFB
RCP CCP1
CCP
VOSEN+ 18 20 VOSEN19 17 16 ROCP3 COCP3 RCS3 SW GATEH 15 14 13 12 11 CVCCL4 CBST3 L3 CCS3
ISHARE
CSIN+
CSIN-
9
PGND
1 2 3 4 5
ILL PSI# DACIN LGND
EAIN
IR3529
PHSOUT
VCC BOOST VCCL GATEL 10 OCSET
PHSIN SHIFT
CLKIN 8
6
7
9
PGND
20
18
19
17
16
ROCP4 COCP4 RCS4 SW GATEH 15 14 13 12 11 CVCCL5 CBST4 L4 CCS4
ISHARE
CSIN+
CSIN-
1 2 3 4 5
ILL PSI# DACIN LGND
EAIN
IR3529
PHSOUT
VCC BOOST VCCL GATEL 10 OCSET
PHSIN SHIFT
CLKIN 8
6
7
Figure 9: Multi Phase Application Circuit
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9
PGND
February 12, 2010
IR3529
DESIGN PROCEDURES - IR3529
Inductor Current Sensing Capacitor CCS and Resistor RCS The DC resistance of the inductor is utilized to sense the inductor current. Usually the resistor RCS and capacitor CCS in parallel with the inductor are chosen to match the time constant of the inductor, and therefore the voltage across the capacitor CCS represents the inductor current. If the two time constants are not the same, the AC component of the capacitor voltage is different from that of the real inductor current. The time constant mismatch does not affect the average current sharing among the multiple phases, but does affect the current signal IOUT as well as the output voltage during the load current transient if adaptive voltage positioning is adopted. Measure the inductance L and the inductor DC resistance RL. Pre-select the capacitor CCS and calculate RCS as follows. L RL (1) RCS = C CS Bootstrap Capacitor CBST Depending on the duty cycle and gate drive current of the phase IC, a capacitor in the range of 0.1uF to 1uF is needed for the bootstrap circuit. Decoupling Capacitors for Phase IC A 0.1uF-1uF decoupling capacitor is required at the VCCL pin. Current Share Loop Compensation The internal compensation of current share loop ensures that crossover frequency of the current share loop is at least one decade lower than that of the voltage loop so that the interaction between the two loops is eliminated. The crossover frequency of current share loop is approximately 8 kHz
Cycle-by-Cycle Over Current Protection
Cycle-by-cycle over current protection helps to improve the transient response at load repetition rates closer to the switching frequency of the VR. The over current threshold is programmed with an external resistor (ROCSET) connected to the OCSET pin with a sink current of 200 A. The OCSET comparator monitors the voltage across the on-resistance (RDS, ON) of the high-side MOSFET and terminates the high side pulse if the sensed voltage reaches the over current threshold. A capacitor (COCSET) is used to reduce noise coupling into the OCSET pin of the IC. ROCSET =
(Iload _ per _ phase * Rds, on )
200
where Iload_per_phase is the maximum current per phase which you do not want to exceed.
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February 12, 2010
IR3529
LAYOUT GUIDELINES
The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB layout; therefore, minimizing the noise coupled to the IC.
* Dedicate at least one middle layer for a ground plane, which is then split into signal ground plane (LGND) and power ground plane (PGND). * Separate analog bus (EAIN, DACIN, and IOUT) from digital bus (CLKIN, PSI, PHSIN, and PHSOUT) to reduce the noise coupling. * Connect PGND to LGND pins of each phase IC to the ground tab, which is tied to LGND and PGND planes respectively through vias. * Place current sense resistors and capacitors (RCS and CCS) close to phase IC. Use Kelvin connection for the inductor current sense wires, but separate the two wires by ground polygon. The wire from the inductor terminal to CSIN- should not cross over the fast transition nodes, i.e., switching nodes, gate drive outputs, and bootstrap nodes. * Place the decoupling capacitors CVCC and CVCCL as close as possible to VCC and VCCL pins of the phase IC respectively. * Place the phase IC as close as possible to the MOSFETs to reduce the parasitic resistance and inductance of the gate drive paths. * Place the input ceramic capacitors close to the drain of top MOSFET and the source of bottom MOSFET. Use combination of different packages of ceramic capacitors. * There are two switching power loops. One loop includes the input capacitors, top MOSFET, inductor, output capacitors and the load; another loop consists of bottom MOSFET, inductor, output capacitors and the load. Route the switching power paths using wide and short traces or polygons; use multiple vias for connections between layers.
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February 12, 2010
IR3529
PCB Metal and Component Placement
* Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be 0.2mm to minimize shorting. * Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension + 0.05mm inboard extension. The outboard extension ensures a large and inspectable toe fillet, and the inboard extension will accommodate any part misalignment and ensure a fillet. * Center pad land length and width should be equal to maximum part pad length and width. However, the minimum metal to metal spacing should be 0.17mm for 2 oz. Copper ( 0.1mm for 1 oz. Copper and 0.23mm for 3 oz. Copper). * Four 0.3mm diameter vias shall be placed in the pad land spaced at 1.2mm, and connected to ground to minimize the noise effect on the IC and to transfer heat to the PCB. * No PCB traces should be routed nor vias placed under any of the 4 corners of the IC package. Doing so can cause the IC to rise up from the PCB resulting in poor solder joints to the IC leads.
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February 12, 2010
IR3529
Solder Resist
* The solder resist should be pulled away from the metal lead lands and center pad by a minimum of 0.06mm. The solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non Solder Mask Defined (NSMD). Therefore, pulling the S/R 0.06mm will always ensure NSMD pads. * The minimum solder resist width is 0.13mm. At the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a fillet so a solder resist width of 0.17mm remains. * Ensure that the solder resist in-between the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. * The 4 vias in the land pad should be tented with solder resist 0.4mm diameter, or 0.1mm larger than the diameter of the via.
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February 12, 2010
IR3529
Stencil Design
* The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release. * The stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead land. * The land pad aperture should be striped with 0.25mm wide openings and spaces to deposit approximately 50% area of solder on the center pad. If too much solder is deposited on the center pad the part will float and the lead lands will be open. * The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste.
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February 12, 2010
IR3529
PACKAGE INFORMATION
20L MLPQ (4 x 4 mm Body) - JA = 36 C/W, JC = 3.6 C/W
o o
Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. Page 22 of 22 February 12, 2010

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